SEMICONDUCTOR MEMORY DEVICE FOR CONTROLLING CLOCK DOMAIN CHANGE

摘要

A semiconductor memory device is provided, which controls the clock domain change according to data training by regularly maintaining the domain change margin regardless of the mode selection. A first signal control unit delays the first clock signal as the first time and outputs it by being supplied with the first input signal in response to the delayed first clock signal. The second signal control unit delays the second clock signal as the second time and outputs it by being supplied with the second input signal in response to the delayed second clock signal. The third signal control unit delays the output signal of the second signal control unit as the third time and outputs it. The output signal of the dummy delay part is input into the signal processing part.