| 摘要 |
A method for forming a test pattern of a semiconductor device is provided to obtain an accurate value in a test process by preventing sidewall stress of an isolation layer due to mobile ions. A gate pattern is formed on an upper surface of a semiconductor substrate(100). A junction region(108) is formed in a region which is separated by the gate pattern and an isolation layer(107). A first contact and a second contact are formed to be connected with the gate pattern and the junction region, respectively. A test probe comes in contact with the first contact and the second contact, respectively. The gate pattern is formed by laminating sequentially a tunnel insulating layer(101), a conductive layer for floating gate(102), a dielectric layer(103), a conductive layer(104) for control gate, and a metal gate layer(105). The conductive layer for control gate penetrates the dielectric layer in order to be electrically connected with the conductive layer for floating gate.
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