发明名称 |
HAZARD COUNTERMEASURE CIRCUIT, OUTPUT CIRCUIT AND SEMICONDUCTOR DEVICE |
摘要 |
PROBLEM TO BE SOLVED: To provide a hazard countermeasure circuit suppressing an increase in power consumption during normal operation by stabilizing an output of a circuit when the power is supplied or shut off, and to provide an output circuit and a semiconductor device. SOLUTION: The first power and the second power which are started before and/or after the first power are supplied to the hazard countermeasure circuit. The hazard countermeasure circuit is provided with an inverter which uses the first power for a power supply voltage and an N channel MOS transistor in which an output of the inverter is connected to a gate. The N channel MOS transistor connects an output terminal of an output circuit with a reference terminal. This prevents hazard appearing in an output circuit of a circuit when the power is supplied or/and shut off. The power consumption of the circuit is not increased during normal operation. COPYRIGHT: (C)2009,JPO&INPIT
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申请公布号 |
JP2009141396(A) |
申请公布日期 |
2009.06.25 |
申请号 |
JP20070312283 |
申请日期 |
2007.12.03 |
申请人 |
FUJITSU MICROELECTRONICS LTD |
发明人 |
MIURA TETSUYA |
分类号 |
H03K17/16;H03K17/22;H03K17/687;H03K19/0175;H03K19/0185;H03K19/0948 |
主分类号 |
H03K17/16 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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