EMBEDDED STRUCTURE FOR PASSIVATION INTEGRITY TESTING

摘要

The present invention relates to a method and system for testing integrity of a passivation layer (108) covering a semiconductor device. A structured layer of electrically conducting material (104) is deposited onto at least a portion of a top surface of a substrate (102) of the semiconductor device. The structured layer (104) comprises a plurality of bands (104.1, 104.2) connected to at least two contacts (106.1, 106.2) and disposed on the at least a portion of the top surface such that one of consecutive bands (104.1, 104.2) and consecutive portions of the bands (104.1, 104.2) are connected to different contacts (106.1, 106.2). A passivation layer (108) is deposited onto the at least a portion of the top surface of the substrate (102) and the structured layer (104) such that material of the passivation layer(108) is disposed between the bands of conducting material (104.1, 104.2) and on top of the structured layer (104). Electrically conducting material is then deposited onto the passivation layer (108) and a resistance is measured between the at least two contacts (106.1, 106.2). An indication with respect to integrity of the passivation layer (108) is determined in dependence upon the measured resistance.