发明名称 MEMORY TESTING SYSTEM
摘要 PROBLEM TO BE SOLVED: To provide a memory testing system which can detect a new fail while regulating performance degradation. SOLUTION: The memory testing system 1 includes an interleave controller 10, a fail information storing section 20, a logical OR section 30, a memory for analysis 40, and a repair calculating section 50. Among them, the fail information storing section 20 includes sub memories 21c and 22c for reading the fail information logical ORed by the logical OR section 30 to store. The fail information storing section 20 determines the fail information sent from the interleave controller 10 as the new fail or not in accordance with the information stored in the sub memories 21c and 22c, and sends the fail information to the logical OR section 30 while storing the fail information in the internal memories 21b and 22b when determining as the new fail. COPYRIGHT: (C)2009,JPO&INPIT
申请公布号 JP2009140548(A) 申请公布日期 2009.06.25
申请号 JP20070314291 申请日期 2007.12.05
申请人 YOKOGAWA ELECTRIC CORP 发明人 MURATA MICHIO
分类号 G11C29/56;G01R31/28 主分类号 G11C29/56
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