| 摘要 |
<p>A semiconductor device and a manufacturing method thereof are provided to prevent a leaning effect of a pillar pattern by enhancing transfer efficiency of a driving voltage of each transistor within a transistor array having upper/lower channels. A semiconductor device includes a plurality of transistors(100) which are formed in upper/lower directions. The transistor includes a pillar pattern(42), a gate insulating layer(43) formed on a sidewall of the pillar pattern, and a conductive layer(44) formed on a sidewall of the gate insulating layer. The transistor further includes a source and a drain which are formed on the pillar pattern and are in contact with upper/lower parts of the conductive layer. The transistor includes a buried bit line(45) formed at a lower part of the pillar pattern. The pillar pattern is formed by etching a substrate(41) or performing a deposition and patterning process.</p> |
