发明名称 BIAS VOLTAGE CIRCUIT AND PHASE LOCKED LOOP
摘要 A bias voltage circuit and phase locked loop are provided to shorten jitter peking to have phase margin by controlling the band width of bias voltage generation circuit. A bias circuit(100) controls current based on band width control signal. An amplifying device(200) amplifies input signal with regulated current from bias control circuit as an operating current. An output device(300) outputs a vias control voltage responding to the output signal of amplifying device.
申请公布号 KR20090067469(A) 申请公布日期 2009.06.25
申请号 KR20070135145 申请日期 2007.12.21
申请人 HYNIX SEMICONDUCTOR INC. 发明人 SONG, TAEK SANG;KIM, KYUNG HOON;KWON, DAE HAN;YOON, DAE KUN
分类号 G05F3/24 主分类号 G05F3/24
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