发明名称 MASK PATTERN CORRECTION METHOD AND EXPOSURE MASK
摘要 <P>PROBLEM TO BE SOLVED: To provide a mask pattern correction method which can conduct high speed simulation for a mask pattern including both hole patterns and space patterns even when making OPC considering the mask 3D effects, and also provide an exposure mask thereof. <P>SOLUTION: This mask pattern correction method forms an evaluation pattern (S1), produces an evaluation mask having the evaluation patterns (S2), and forms a wafer pattern by using this evaluation mask (S3). After measuring the dimensions of the wafer pattern (S4), it compute the errors between the simulated values obtained through the exposure simulation using the evaluation pattern and the actually measured pattern sizes, and optimizes the simulation parameters containing at least the bias value (&Delta;1) at the corners (2a, 2b) of the hole patterns and space patterns (1) and the bias value (&Delta;2) at the sides (3a, 3b) in order to make these errors small, then produces the OPC model (S5). <P>COPYRIGHT: (C)2009,JPO&INPIT
申请公布号 JP2009139632(A) 申请公布日期 2009.06.25
申请号 JP20070315787 申请日期 2007.12.06
申请人 ELPIDA MEMORY INC 发明人 YASUSATO TADAO
分类号 G03F1/32;G03F1/36;G03F1/68;H01L21/027 主分类号 G03F1/32
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