CLOCK SIGNAL GENERATION CIRCUIT, DISPLAY PANEL MODULE, IMAGING DEVICE AND ELECTRONIC APPARATUS

摘要

PROBLEM TO BE SOLVED: To solve the problem wherein a manufacturing cost is increased in a conventional clock signal generation circuit because its circuit scale is large.

SOLUTION: A delay synchronous loop type clock signal generation circuit comprises: a delay line for delaying a first clock signal only by a set delay amount and outputting the first clock signal; a delay time length setting unit for setting the delay time length of the delay line on the basis of a phase difference between a second clock signal outputted from an output terminal and the first clock signal; a phase relation determining unit for detecting whether the phase relation between the first clock signal and the second clock signal has a specific phase relation; and a phase inverting/noninverting unit for inverting the phase of the first clock signal on a propagation path including the delay line when the specific phase relation is detected.

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