发明名称 |
FORMING ROBUST SOLDER INTERCONNECT STRUCTURES BY REDUCING EFFECTS OF SEED LAYER UNDERETCHING |
摘要 |
A method for forming an interconnect structure for a semiconductor device includes defining a via in a passivation layer so as expose a top metal layer in the semiconductor device. A seed layer is formed over the passivation layer, sidewalls of the via, and the top metal layer. A barrier layer is formed over an exposed portion of the seed layer, the exposed portion defined by a first patterned opening of a first diameter, and a solder material is formed over the barrier layer using a second patterned opening of a second diameter. The second patterned opening is configured such that the second diameter is larger than the first diameter.
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申请公布号 |
US2009163019(A1) |
申请公布日期 |
2009.06.25 |
申请号 |
US20090348143 |
申请日期 |
2009.01.02 |
申请人 |
INTERNATIONAL BUSINESS MACHINES CORPORATION |
发明人 |
SRIVASTAVA KAMALESH K.;SHINDE SUBHASH L.;CHENG TIEN-JEN;KNICKERBOCKER SARAH H.;QUON ROGER A.;SABLINSKI WILLIAM E.;BIGGS JULIE C.;EICHSTADT DAVID E.;GRIFFITH JONATHAN H. |
分类号 |
H01L21/44;H01L21/48;H01L23/485 |
主分类号 |
H01L21/44 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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