发明名称 CIRCUIT ANALYSIS METHOD, CIRCUIT ANALYSIS PROGRAM AND CIRCUIT ANALYSIS APPARATUS
摘要 PROBLEM TO BE SOLVED: To reduce a circuit area of a semiconductor device to be designed. SOLUTION: This circuit analysis apparatus 30 is provided with a storage device 33 for storing a package model 1, a noise source model 3, a noise-subjected circuit model 2, and a substrate model 4 which are lumped constant circuits, and a noise analysis part 108 for generating an analysis target circuit model 200 by connecting the package model 1, the noise source model 3, the noise-subjected circuit model 2, and the substrate model 4. The noise analysis part 108 applies circuit simulation to the analysis target circuit model 200 to calculate and output a power supply voltage waveform in a noise-subjected circuit. COPYRIGHT: (C)2009,JPO&INPIT
申请公布号 JP2009140216(A) 申请公布日期 2009.06.25
申请号 JP20070315675 申请日期 2007.12.06
申请人 NEC ELECTRONICS CORP 发明人 KOBAYASHI SUSUMU
分类号 G06F17/50;H01L21/82 主分类号 G06F17/50
代理机构 代理人
主权项
地址