发明名称
摘要 A method of low latency encoding of an input bit sequence (S0) to yield an encoded bit sequence (S), and a corresponding decoding method, said encoding method including: a first encoding step (E1) applied to bits of the input bit sequence (S0), using a first code; an interleaving step (E3) in which an interleaver interleaves the bits obtained from said first code; and a parity, second encoding step (E4) applied to the bits obtained from said interleaver, using a second code, to generate said encoded bit sequence (S). The parity, second encoding step (E4) starts after a predetermined numberΔof bits have been interleaved, said predetermined numberΔof bits ranging between a first lower numberΔi of bits depending on one or more parameters of said interleaving step (E3) and a first higher numberΔs of bits corresponding to the total number of bits to be processed during said interleaving step (E3).
申请公布号 JP2009524316(A) 申请公布日期 2009.06.25
申请号 JP20080550822 申请日期 2007.01.18
申请人 发明人
分类号 H03M13/19;H03M13/27;H03M13/29 主分类号 H03M13/19
代理机构 代理人
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