发明名称 Compact Power Semiconductor Package and Method with Stacked Inductor and Integrated Circuit Die
摘要 A power semiconductor package is disclosed with high inductance rating while exhibiting a reduced foot print. It has a bonded stack of power IC die at bottom, a power inductor at top and a circuit substrate, made of leadframe or printed circuit board, in the middle. The power inductor has a inductor core of closed magnetic loop. The circuit substrate has a first number of bottom half-coil forming conductive elements beneath the inductor core. A second number of top half-coil forming conductive elements, made of bond wires, three dimensionally formed interconnection plates or upper leadframe leads, are located atop the inductor core with both ends of each element connected to respective bottom half-coil forming conductive elements to jointly form an inductive coil enclosing the inductor core. A top encapsulant protectively encases the inductor core, the top half-coil forming conductive elements, the bottom half-coil forming conductive elements and the circuit substrate.
申请公布号 US2009160595(A1) 申请公布日期 2009.06.25
申请号 US20090391251 申请日期 2009.02.23
申请人 FENG TAO;ZHANG XIAOLIAN;HEBERT FRANCOIS;SUN MING 发明人 FENG TAO;ZHANG XIAOLIAN;HEBERT FRANCOIS;SUN MING
分类号 H01F5/00;H01L21/60;H01L23/495 主分类号 H01F5/00
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