IMPROVING MEMORY READ STABILITY USING SELECTIVE PRECHARGE OF BIT LINE SECTIONS
摘要
<p>A memory device utilizes selective precharge and charge sharing to reduce a bit line voltage before accessing a bit cell (34). A reduction in bit line voltage is achieved by precharging different sections (31, 33) of the bit line to different voltages (e.g., a supply voltage and ground) and using charge sharing between these sections. Read stability improves as a result of the reduction of bit line voltage. The relative capacitance difference (B2-C2) between bit line sections determines the bit line voltage after charge sharing. Thus, the memory device is tolerant to process or temperature variations. The bit line voltage may be controlled in design by selecting the sections that are precharged to supply voltage or ground.</p>
申请公布号
WO2009079455(A1)
申请公布日期
2009.06.25
申请号
WO2008US86829
申请日期
2008.12.15
申请人
QUALCOMM INCORPORATED;ABU-RAHMA, MOHAMED H.;CHABA, RITU;CHEN, NAN;YOON, SEI SEUNG
发明人
ABU-RAHMA, MOHAMED H.;CHABA, RITU;CHEN, NAN;YOON, SEI SEUNG