CLOCK SIGNAL GENERATION CIRCUIT, DISPLAY PANEL MODULE, IMAGING DEVICE AND ELECTRONIC APPARATUS

摘要

PROBLEM TO BE SOLVED: To solve the problem wherein a manufacturing cost is increased in a conventional clock signal generation circuit because its circuit scale is large.

SOLUTION: A delay synchronous loop type clock signal generation circuit comprises: a digital type delay line for delaying a first clock signal to generate a second clock signal; a ring type shift register for setting the delay time length of the digital type delay line by a flip-flop output of each stage; and a delay amount control unit for controlling the supply of a shift clock for the ring type shift register on the basis of a phase relation between the first clock signal and the second clock signal.

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