发明名称 METHOD AND APPARATUS FOR SUPPORTING DESIGN OF SEMICONDUCTOR INTEGRATED CIRCUIT
摘要 PROBLEM TO BE SOLVED: To reduce a design cost by verifying a risk of simultaneous switching noise due to disposal positions of power supply pads on the initial stage of design. SOLUTION: Power supply pads and input/output pads corresponding to respective I/O cells are temporarily disposed, a package drawing is created on the basis of the coordinates of the power supply pads and the input/output pads, the inductance of the power supply pads is calculated by using the package drawing, and noise risks of respective input/output pads are calculated by using the inductance of the power supply pads and the drive factors of respective I/O cells. The addition, deletion position change, or the like of power supply pads is performed on the basis of the distribution of noise risks. COPYRIGHT: (C)2009,JPO&INPIT
申请公布号 JP2009140225(A) 申请公布日期 2009.06.25
申请号 JP20070315823 申请日期 2007.12.06
申请人 TOSHIBA CORP 发明人 IMADA TOMOHIKO
分类号 G06F17/50;H01L21/82;H01L21/822;H01L27/04 主分类号 G06F17/50
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