| 摘要 |
A test pattern of a semiconductor device and manufacturing method thereof are provided. The test pattern can include an isolation layer on a semiconductor substrate to define an active area, a gate electrode on the active area, and a source/drain area at a first area of the active area between the gate electrode and the isolation layer, a third area of the active area spaced apart from the gate electrode, and a second area of the active area electrically connecting the first area with the third area.
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