发明名称 |
Regulation of Source Potential to Combat Cell Source IR Drop |
摘要 |
Techniques are presented for dealing with possible source line bias is an error introduced by a non-zero resistance in the ground loop of the read/write circuits of a non-volatile memory. The error is caused by a voltage drop across the resistance of the source path to the chip's ground when current flows. For this purpose, the memory device includes a source potential regulation circuit, including an active circuit element having a first input connected to a reference voltage and having a second input connected as a feedback loop that is connectable to the aggregate node from which the memory cells of a structural block have their current run to ground. A variation includes a non-linear resistive element connectable between the aggregate node and ground.
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申请公布号 |
US2009161433(A1) |
申请公布日期 |
2009.06.25 |
申请号 |
US20070961871 |
申请日期 |
2007.12.20 |
申请人 |
LEE DANA;MOKHLESI NIMA;SEKAR DEEPAK CHANDRA |
发明人 |
LEE DANA;MOKHLESI NIMA;SEKAR DEEPAK CHANDRA |
分类号 |
G11C16/10;G11C16/26 |
主分类号 |
G11C16/10 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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