发明名称 Method and program for designing semiconductor integrated circuits, and semiconductor integrated circuit designing apparatus
摘要 Two paths (arrival and required paths) as a target of analysis are united into a single path, and an on-chip random variation component sigmar about a plurality of nodes of the single path is calculated. Next, an on-chip variation component chip is calculated on the basis of the on-chip random variation component sigmar and an on-chip systematic variation component sigmas. Subsequently, a delay variation Docv is calculated on the basis of a reference delay Dbase of the entire path and the on-chip variation component sigmachip.
申请公布号 US2009164958(A1) 申请公布日期 2009.06.25
申请号 US20090379361 申请日期 2009.02.19
申请人 RENESAS TECHNOLOGY CORP. 发明人 YOSHIKAWA ATSUSHI
分类号 G06F17/50 主分类号 G06F17/50
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