发明名称 Multi-threaded packet processing architecture with global packet memory, packet recirculation, and coprocessor
摘要 A network processor has numerous novel features including a multi-threaded processor array, a multi-pass processing model, and Global Packet Memory (GPM) with hardware managed packet storage. These unique features allow the network processor to perform high-touch packet processing at high data rates. The packet processor can also be coded using a stack-based high-level programming language, such as C or C++. This allows quicker and higher quality porting of software features into the network processor. Processor performance also does not severely drop off when additional processing features are added. For example, packets can be more intelligently processed by assigning processing elements to different bounded duration arrival processing tasks and variable duration main processing tasks. A recirculation path moves packets between the different arrival and main processing tasks. Other novel hardware features include a hardware architecture that efficiently intermixes co-processor operations with multi-threaded processing operations and improved cache affinity.
申请公布号 US7551617(B2) 申请公布日期 2009.06.23
申请号 US20050054076 申请日期 2005.02.08
申请人 CISCO TECHNOLOGY, INC. 发明人 EATHERTON WILL;COHEN EARL T.;FINGERHUT JOHN ANDREW;STEISS DONALD E.;WILLIAMS JOHN
分类号 H04L12/56 主分类号 H04L12/56
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