发明名称 Jitter tolerance testing apparatus, systems, and methods
摘要 Apparatus, systems, methods, and articles may operate to move an output phase of a clock phase adjustment device associated with a master clock through a plurality of phase shifts relative to a phase of the master clock. A data integrity test may be performed on a serial data receive circuit clocked using an output phase of the clock phase adjustment device following each one of the plurality of phase shifts.
申请公布号 US7552366(B2) 申请公布日期 2009.06.23
申请号 US20050173145 申请日期 2005.06.30
申请人 INTEL CORPORATION 发明人 KANTER OFIR;PELEG ERAN;SHOOR EHUD;STERIN ELI
分类号 G06K5/04;G06F11/00 主分类号 G06K5/04
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