| 摘要 |
A VLIW digital signal processor is composed of a program memory including first to n-th banks, first to n-th address counters, a fetch block, and an instruction executing section. The first to n-th banks store therein first to n-th programs, respectively. The first to n-th address counters respectively indicates addresses at which next instructions to be executed next, selected out of VLIW instructions within said first to n-th programs, are stored in said first to n-th banks. The fetch block is configured to fetch said next instructions from said addresses, respectively, and to generate a resultant VLIW instruction from said next instructions. The instruction executing section is configured to receive said resultant VLIW instruction, and to execute said resultant VLIW instruction in a single instruction executing cycle.
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