发明名称 Bit line coupling
摘要 The invention provides methods and apparatus. Alternate bit-line pairs of a memory device are concurrently selected. Each bit-line pair has one bit line formed at a first vertical level and one adjacent bit line formed at a second vertical level different than the first vertical level.
申请公布号 US7551466(B2) 申请公布日期 2009.06.23
申请号 US20060360873 申请日期 2006.02.23
申请人 MICRON TECHNOLOGY, INC. 发明人 ARITOME SEIICHI
分类号 G11C5/06 主分类号 G11C5/06
代理机构 代理人
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