发明名称 |
Method and apparatus for testing integrated circuits for susceptibility to latch-up |
摘要 |
In an example embodiment, there is a test module for testing the susceptibility of an integrated circuit design to latch-up. The test module comprises a plurality of test blocks, connected in parallel. Each test block includes an injector block for applying a stress current of voltage to the respective test block and a plurality of sensor blocks located at successively increasing distances from the respective injector block. Each sensor block includes a PNPN latch-up test structure. The present invention combines the respective advantages of IC stress current testing and latch-up parameter measurement using a standard PNPN latch-up test structure.
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申请公布号 |
US7550990(B2) |
申请公布日期 |
2009.06.23 |
申请号 |
US20050587645 |
申请日期 |
2005.01.27 |
申请人 |
NXP B.V. |
发明人 |
SCARPA ANDREA;CAPPON PAUL H.;DE JONG PETER C.;SMEDES TAEDE |
分类号 |
G01R31/26;G01R31/316;G01R31/3161;H01L23/544 |
主分类号 |
G01R31/26 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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