发明名称 Input/output buffer controller for optimized memory utilization and prevention of packet under-run errors
摘要 To avoid under-run conditions that result in corrupt packets at I/O interfaces, a FIFO buffer controller monitors key aspects of the contents of FIFO buffers of I/O interfaces. The FIFO buffer controller initiates transmission of data from the FIFO buffer when at least one complete packet is stored in the FIFO buffer or when the size of a partial packet stored therein is large enough so that the remainder of the packet would normally be received by the FIFO buffer before the stored part can be transmitted from the FIFO buffer; thereby avoiding an under-run error condition.
申请公布号 US2009147796(A1) 申请公布日期 2009.06.11
申请号 US20070000151 申请日期 2007.12.10
申请人 ALCATEL LUCENT 发明人 CHOW JOEY
分类号 H04L12/56 主分类号 H04L12/56
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