| 摘要 |
<p>A computer system for correction of errors in a memory array includes an error correction algorithm and a memory. The error correction algorithm is capable of correcting errors up to a first bit error rate in a correctable group of memory cells having a standard size. The memory is operative to store a first set of ECC bits having information corresponding to a first group of memory cells having a first size larger than the standard size, and to store a second set of ECC bits having information corresponding to a second group of memory cells having a second size smaller than said first size and being a portion of said first group. The error correction algorithm is operative to correct errors in the second group based on the second set of ECC bits if a failure occurs in correction of the first group based on the first set of ECC bits.</p> |
