发明名称 |
Logic circuit delay optimization |
摘要 |
A method for modifying a logic circuit layout to optimize circuit propagation delays for improved circuit operation is presented. The layout includes multiple logic gates connected by conductive segments. An initial layout of a physical electronic logic circuit having the plurality of logic gates is input. A respective size is determined for each of the logic gates in accordance with the initial layout and a circuit propagation delay criterion. The circuit propagation delay criterion is a joint function of properties of at least some of the logic gates and at least some of the conductive segments. A modified logic circuit layout is output. The modified logic circuit layout includes a layout of the logic gates arranged in accordance with the initial layout, where each of the logic gates is modified according to the respective determined size, thereby to obtain a modification of the logic circuit layout incorporating an optimized circuit propagation delay.
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申请公布号 |
US2009150847(A1) |
申请公布日期 |
2009.06.11 |
申请号 |
US20080292931 |
申请日期 |
2008.12.01 |
申请人 |
TECHNION RESEARCH & DEVELOPMENT FOUNDATION LTD. |
发明人 |
MORGENSHTEIN ARKADIY;GINOSAR RAN;KOLODNY AVINOAM;FRIEDMAN EBY G. |
分类号 |
G06F17/50 |
主分类号 |
G06F17/50 |
代理机构 |
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地址 |
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