| 摘要 |
A balanced program rate on NVM cells is achieved by (i) scrambling data bits and user bits; and (ii) shifting ED bits (of data and user bits) according to an incremental shift number, which may be the PBE-counter (which provides an incremental number). ED bits for the LSS may also be shifted, according to an incremental shift number (which may be the PBE-counter). The ED bits of the shift-niumber inherently have an evenly balanced distribution The ED bits of the PBE-counter inherently have an evenly balanced distribution.
|
