发明名称 SYSTEM IN PACKAGE AND FABRICATION METHOD THEREOF
摘要 There is provided a system-in-package including: a substrate of a sawed base wafer on which a semiconductor circuit is formed; a conductive post formed on a top surface of the substrate; at least one semiconductor chip stacked on the top surface of the substrate; a buried layer formed on the top surface of the substrate so as to cover at least partially the conductive post and the semiconductor chip; and an external connection bump electrically connected to the conductive post. The system-in-package is fabricated by stacking a plurality of semiconductor chips on a top surface of a base wafer, forming a buried layer, realizing an electrical path by a conductive post, and polishing top and bottom surfaces of the package, thereby thinning the thickness of the package. Further, the system-in-package greatly improves electrical operation characteristics and increases productivity.
申请公布号 US2009146281(A1) 申请公布日期 2009.06.11
申请号 US20080111892 申请日期 2008.04.29
申请人 NEPES CORPORATION 发明人 JUNG GI JO
分类号 H01L23/00;H01L21/50 主分类号 H01L23/00
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