BIT-PARALLEL MULTIPLIER AND MULTIPLYING METHOD FOR FINITE FIELD USING REDUNDANT REPRESENTATION

摘要

A finite field bit-parallel multiplier using redundant expressions and a method therefor are provided to reduce the spatial complexity as efficiently operating in the exponential multiplication environment. A subtraction matrix generating unit(100) generates a subtraction matrix by performing the subtraction process of a matrix which is defined to perform the polynomial multiplication. The matrix consists of polynomial coefficients of the first element which is expressed through the redundant representation. An inner product unit(110) inner-products a matrix of the second element and the subtraction matrix generated by the subtraction matrix generating unit. The matrix of the second element has polynomial coefficients which are expressed through polynomial basis the as components.