发明名称 CLOCK GENERATION CIRCUIT
摘要 <p><P>PROBLEM TO BE SOLVED: To provide a clock generation circuit capable of generating a clock signal of which the frequency is fluctuated at all times, in simple circuit configuration. <P>SOLUTION: The clock generation circuit includes: a ring oscillator 11 in which an odd-number of inverters inv1-invN connected in series are included, the output of the final-stage inverter invN is input to the first-stage inverter inv1 and a clock signal is generated and output; a frequency divider circuit 12 in which the clock signal output from the ring oscillator 11 is given, frequency-divided and output; and a heater 14 which is on-off controlled according to the output of the frequency divider circuit 12 and heats the ring oscillator 11 during ON. <P>COPYRIGHT: (C)2009,JPO&INPIT</p>
申请公布号 JP2009130715(A) 申请公布日期 2009.06.11
申请号 JP20070304711 申请日期 2007.11.26
申请人 TOSHIBA CORP 发明人 KANEKO YOSHIO
分类号 H03K3/03;G06F1/06;H03K3/354 主分类号 H03K3/03
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