| 摘要 |
<p><P>PROBLEM TO BE SOLVED: To provide a clock signal generation circuit capable of generating high-speed clock signals from a low-speed reference clock and mitigating the limit of the frequency selection of the high-speed clock signals by a simple circuit configuration. <P>SOLUTION: The clock signal generation circuit 100 includes, in the order, a reference clock signal generation circuit 110 for generating a low-speed reference clock signal S1, a PLL circuit 130 for multiplying the low-speed reference clock signal S1 from the basic clock signal generation circuit 110 by N1 and outputting multiple output S2, a frequency divider circuit 140 for frequency-dividing the multiple output S2 of the PLL circuit 130 by 1/N and outputting a second reference clock signal S3 faster than the low-speed reference clock signal S1, and a PLL circuit 150 for multiplying the second reference clock signal S3 of the frequency divider circuit 140 by N2 and outputting multiple output S4 which is the high-speed clock signal. <P>COPYRIGHT: (C)2009,JPO&INPIT</p> |
