| 摘要 |
<P>PROBLEM TO BE SOLVED: To align parallel data in accordance with bit shift of a synchronizing pattern, in simple circuit configuration, without increasing a circuit scale, power consumption and latency. <P>SOLUTION: A synchronizing pattern is detected by a synchronizing pattern detection circuit 107 using data 161-165, 261-265 after serial-to-parallel conversion. When the bit shift is present, a HOLD signal 105 is generated in accordance with the amount of the bit shift, and input to a data selection circuit 119. The data selection circuit 119 generates a data shift circuit 106 from the HOLD circuit 105, performs data route selection and simultaneously inputs the data shift signal 106 to a clock frequency divider circuit 6. The data shift circuit 106 delays the phase of a frequency dividing clock 103 to delay timing of data retiming of serial-to-parallel conversion circuits 115, 116. <P>COPYRIGHT: (C)2009,JPO&INPIT |
