发明名称 Processor and Signal Processing Method
摘要 This invention combines a loop support mechanism and a branch prediction mechanism. After an instruction execution unit executes an end block instruction of a block repeat, the loop control unit branches to the first instruction in the loop and sends a pseudo branch instruction to the instruction execution unit. The instruction execution unit acts as if the last instruction in the block is an instruction for branching to the start address of the block. This is stored in the branch prediction unit and branch prediction is performed thereafter.
申请公布号 US2009150658(A1) 申请公布日期 2009.06.11
申请号 US20080329103 申请日期 2008.12.05
申请人 MIZUMO HIROYUKI 发明人 MIZUMO HIROYUKI
分类号 G06F9/38 主分类号 G06F9/38
代理机构 代理人
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