CLOCK SIGNAL GENERATING CIRCUIT, DISPLAY PANEL MODULE, IMAGING DEVICE, AND ELECTRONIC EQUIPMENT

摘要

A delay synchronization loop type clock signal generating circuit includes: a digital delay line for delaying a first clock signal and generating a second clock signal; a ring-type shift register for setting the delay time length of the digital delay line by flip-flop output of each stage thereof; and a delay amount control unit for controlling supply of shift clocks to the ring-type shift register, based on phase relation between the first clock signal and the second clock signal.