CHECKING AN ESD BEHAVIOR OF INTEGRATED CIRCUITS ON THE CIRCUIT LEVEL

摘要

A system and a method for checking the ESD behavior, wherein a circuit (7) is automatically checked on the circuit plan level, in that technology-specific ESD data are provided in a database (2) for all components occurring in the circuit and are used for analyzing the ESD behavior, without complex circuit simulations being necessary, for example, based on front end or back end data, in consideration of the layout.