HIGH PERFORMANCE SEMICONDUCTOR MEMORY DEVICES

摘要

High performance memory device have been realized by apjjling Evenly Scaled Multiple Level Architecture (ESMLA) using block select arrangement. A single-bit4ine-write (SBLW) mechanism (805) allows us to reduce the number of bit lines (BL) by 50% for static memory device (801). The resulting memory device can be as fast as registers files while its area is smaller than prior art high density memory devices. The scaling method of the memory architecture also assures that the speed of the memory devices will scale in the same rate as logic circuit in future IC manufacture technologies.