| 摘要 |
A delay locked loop circuit (DLL) is provided. The delay locked loop circuit includes a shift register, a digital-to-analog converter and a voltage controlled delay line. The shift register outputs a digital signal in accordance with a phase difference between an input signal and a feedback signal. The digital-to-analog converter transfers the digital signal output from the shift register into a control voltage. The voltage controlled delay line outputs the feedback signal in accordance with the control voltage transferred by the digital-to-analog converter. A method for eliminating jitter and offset between an input signal and an output signal in a delay locked loop circuit is also disclosed.
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