发明名称 CONTROLLING THREADING DISLOCATION DENSITIES USING GRADED LAYERS AND PLANARIZATION
摘要 <p>A semiconductor structure including a semiconductor substrate, at least one first crystalline epitaxial layer on the substrate, the first layer having a surface which is planarized, and at least one second crystalline epitaxial layer on the at least one first layer. In another embodiment of the invention there is provided a semiconductor structure including a silicon substrate, and a GeSi graded region grown on the silicon substrate, compressive strain being incorporated in the graded region to offset the tensile strain that is incorporated during thermal processing. In yet another embodiment of the invention there is provided a semiconductor structure including a semiconductor substrate, a first layer having a graded region grown on the substrate, compressive strain being incorporated in the graded region to offset the tensile strain that is incorporated during thermal processing, the first layer having a surface which is planarized, and a second layer provided on the first layer. In still another embodiment of the invention there is provided a method of fabricating a semiconductor structure including providing a semiconductor substrate, providing at least one first crystalline epitaxial layer on the substrate, and planarizing the surface of the first layer.</p>
申请公布号 EP1016129(B2) 申请公布日期 2009.06.10
申请号 EP19980931529 申请日期 1998.06.23
申请人 MASSACHUSETTS INSTITUTE OF TECHNOLOGY 发明人 FITZGERALD, EUGENE, A.
分类号 H01L21/20 主分类号 H01L21/20
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