发明名称 |
Direct memory access channel controller with quick channels, event queue and active channel memory protection |
摘要 |
A data transfer control apparatus includes a channel controller and a transfer controller. The channel controller receives, prioritizes and queues event signals and predetermined memory writes which trigger data transfer requests controlling the transfer controller. The event queue stores event numbers mapped to parameter memory locations storing data transfer parameters. The mapping table and the parameter memory are writeable via a memory mapped write operation. Memory protection registers store data indicative of permitted data accesses to the memory map.
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申请公布号 |
US7546391(B2) |
申请公布日期 |
2009.06.09 |
申请号 |
US20060383045 |
申请日期 |
2006.05.12 |
申请人 |
TEXAS INSTRUMENTS INCORPORATED |
发明人 |
CASTILLE ROGER K.;SESHAN NATARAJAN KURIAN;LAZAR MARCO;ZBICIAK JOSEPH R. |
分类号 |
G06F13/28;G06F12/00;G06F13/36;G06F15/167 |
主分类号 |
G06F13/28 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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