| 摘要 |
A clock control circuit including a divider unit for dividing a master clock signal at a falling timing of the same to generate a divided clock signal, a multiplier unit for multiplying the master signal by n at a rising timing of the same, and thinning out an n-th clock pulse to generate a multiplied clock signal, and a selector unit for selecting a bus clock signal from multiplied clock signals at a variety of timings, derived from the multiplied clock signal, and the divided clock signal in accordance with a selection signal, and supplying the selected signal to a processor.
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