| 摘要 |
A well bias circuit in a memory device includes a well voltage supplying circuit configured to apply a high voltage to a well for erasing data in a memory cell. A well discharging circuit is configured to discharge the high voltage applied to the well in accordance with a first control signal after the data in the memory cell is erased. A well-to-ground circuit is configured to control the well bias to obtain a ground voltage in accordance with a second control signal. A control circuit is configured to activate the well discharging circuit for a predetermined time when power is turned on.
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