Trench liner for DSO integration

摘要

A semiconductor process and apparatus provide a shallow trench isolation region (96) with a trench liner (95, 104) for use in a hybrid substrate device (21) by lining a first trench with a first trench liner (95), and then lining a second trench formed within the first trench by depositing a second trench liner (104) that is anisotropically etched to expose an underlying substrate (70) on which is epitaxially grown a silicon layer (110) to fill the second trench. By forming first gate electrodes (251) over a first SOI substrate (90) using deposited (100) silicon and forming second gate electrodes (261) over an epitaxially grown (110) silicon substrate (110), a high performance CMOS device is obtained which includes high-k metal PMOS gate electrodes (261) having improved hole mobility.