| 摘要 |
A semiconductor device and a method for manufacturing thereof is provided to reduce parasitic capacitance between a source region, a drain region, and contact plug by expanding valid area of the source and the drain region through control of the position of a gate electrode. A gate electrode(30) is formed on a semiconductor substrate, and a spacer is formed at the side wall of the gate electrode. A source region(60) and a drain region(70) are formed on the semiconductor substrate of both sides of the gate electrode. An insulating layer is arranged on the processed substrate, and a contact plug is connected to a gate electrode, the source region, and the drain region. A source region(65) includes an additional source region which is expanded from the reside of the gate.
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