| 摘要 |
<P>PROBLEM TO BE SOLVED: To provide a data processor that reduces the reconfiguration time of a reconfigurable logic circuit and can speed up data processing. <P>SOLUTION: A circuit information source 15 holds differential circuit information W(A→B) of a logic circuit B to a logic circuit A. A logic reconfiguration control section 16 reconfigures the logic circuit A in a reconfigurable logic circuit 12 and executes processing left to the logic circuit A. Then, when configuring the logic circuit B in the reconfigurable logic circuit 12, the logic reconfiguration control section 16 reads the differential circuit information W(A→B) of the logic circuit B to the logic circuit A from the circuit information source 15 and transfers information at an address that needs to be reconfigured in the reconfigurable logic circuit 12 and circuit information at an address to be reconfigured to a circuit information holding register 19. <P>COPYRIGHT: (C)2009,JPO&INPIT |
