| 摘要 |
PROBLEM TO BE SOLVED: To provide an operation timing verification device and a program for suppressing a design time or costs while achieving accurate operation timing verification in the design of a semiconductor integrated circuit. SOLUTION: The operation timing verification device and program are provided to extract an operation violation circuit path from circuit layout by setting unrealistic corner conditions in which all delay elements give the maximum delay as operating conditions, and performing operation timing analytic processing, and to execute the operation timing analytic processing only to the operation violation circuit path by setting the unrealistic corner conditions in which the delay elements belonging to at least one element type among the delay elements give the maximum delay as the operating conditions, and to redetermine the presence/absence of the operation violation. COPYRIGHT: (C)2009,JPO&INPIT
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