| 摘要 |
PROBLEM TO BE SOLVED: To provide a semiconductor device having high electrostatic discharge (ESD) resistance. SOLUTION: As shown in Fig.3, in the semiconductor device 1 in which a CMOS region and a DMOS region are formed on a P-type substrate 2, an N-type epitaxial layer 3 is formed on the P-type substrate 2, a P-type well 8 is formed thereon, and an N<SP>+</SP>-type source layer 12 and a drain layer 13 are formed on the surface layer of the P-type well 8. An N-type base layer 31 and a deep N-type base layer 32 are formed on a region immediately below the drain layer 13, and a P-type base layer 33 and a deep P-type base layer 34 are formed on a region immediately below the source layer 12. By this configuration, a punch-through voltage V<SB>PT</SB>of the P-type well 8 disposed between the deep N-type base layer 32 and the N-type epitaxial layer 3 can be set to be lower than an operation voltage V<SB>t1</SB>of a parasitic lateral bipolar transistor 42 composed of the source layer 12, the P-type well 8 and the drain layer 13. COPYRIGHT: (C)2009,JPO&INPIT
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