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发明名称
Verfahren und Vorrichtung zum Quantifizieren des Zeitgebungsfehlers, induziert durch eine Impedanzabweichung eines Signalwegs
摘要
申请公布号
DE102005055829(B4)
申请公布日期
2009.06.04
申请号
DE200510055829
申请日期
2005.11.23
申请人
VERIGY (SINGAPORE) PTE. LTD.
发明人
MATSUMIYA, HIROSHI
分类号
H04L25/12
主分类号
H04L25/12
代理机构
代理人
主权项
地址
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