发明名称 HIGH-DYNAMIC RANGE LOW RIPPLE VOLTAGE MULTIPLIER
摘要 A voltage multiplier (10) including a first clocked multiplier stage (12) having an input and an output and a second clocked multiplier stage (14, 16) having an input and an output is provided. The voltage multiplier further includes an input level regulator (18) coupled to the input of the first multiplier stage. The voltage multiplier further includes a feedback bias control circuit (32) coupled to the input level regulator, wherein the feedback bias control circuit is further coupled to receive the output (50) of the second multiplier stage, and wherein the feedback bias control circuit generates a feedback signal (58) affecting an output of the input level regulator based on a comparison between a voltage proportional to a voltage at the output of the second clocked multiplier stage and a reference voltage.
申请公布号 US2009140795(A1) 申请公布日期 2009.06.04
申请号 US20070948005 申请日期 2007.11.30
申请人 CHOY JON S 发明人 CHOY JON S.
分类号 G05F1/10 主分类号 G05F1/10
代理机构 代理人
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