发明名称 CLOCK DITHERING PROCESS FOR REDUCING ELECTROMAGNETIC INTERFERENCE IN D/A CONVERTERS AND APPARATUS FOR CARRYING OUT SUCH PROCESS
摘要 A process and apparatus for generating an output signal whose frequency varies according to a modulation scheme, the process including the steps of providing a dither generator for receiving a first input signal representative of a clock frequency and for generating, according to the modulation scheme, a dithered output signal representative of the first signal at a dithered frequency; providing a DSP for receiving the following input signals: the signal at the dithered frequency and a second signal representative of a clock frequency, the DSP adapted to generate a processed output signal representative of the maximum frequency of the second signal; wherein the modulation scheme has a periodic ultrasonic modulating wave.
申请公布号 US2009140896(A1) 申请公布日期 2009.06.04
申请号 US20080275871 申请日期 2008.11.21
申请人 STMICROELECTRONICS S.R.L. 发明人 ADDUCI PIETRO MARIO;BOTTI EDOARDO;GONANO GIOVANNI
分类号 H03M1/66 主分类号 H03M1/66
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